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mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis m5m5v408b## -85lw m5m5v408b## -10lw m5m5v408b## -85hw m5m5v408b## -10hw m5m5v408b## -85l m5m5v408b## -10l m5m5v408b## -85h m5m5v408b## -10h m5m5v408b## -85li m5m5v408b## -10li m5m5v408b## -85hi m5m5v408b## -10hi standard 0 ~ +70? w- version -20 ~ +85? i- version -40 ~ +85? version, part name (## stands for "fp","tp", "rt","kv"or"kr") power supply access time max. 25? stand-by current icc (pd) , vcc=3.0v 85ns 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v 2.7 ~ 3.6v --- --- --- 0.3? 0.3? 0.3? --- 1? 1? 3? 1? 3? typical * --- --- --- 40? 1? 1? 1? --- --- 20? 10? 20? 10? 40? 20? 20? 10? 40? 20? 70? 85? 25? 40? --- --- --- --- --- 3? 100ns 85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns description ?single +2.7~+3.6v power supply ?small stand-by current: 0.3?(3v,typ.) ?no clocks, no refresh ?data retention supply voltage=2.0v to 3.6v ?all inputs and outputs are ttl compatible. ?easy memory expansion by s ?common data i/o ?three-state outputs: or-tie capability ?oe prevents data contention in the i/o bus ?process technology: 0.25? cmos ?package: m5m5v408bfp: 32 pin 525 mil sop m5m5v408btp/rt: 32 pin 400mil tsop(ll) m5m5v408bkv/kr: 32 pin 8mm x13.4mm stsop features active current 30ma (10mhz) 5ma (1mhz) ratings (max.) 1 operating temperature the m5m5v408b is a family of low voltage 4-mbit static rams organized as 524,288-words by 8-bit, fabricated by mitsubishi's high- performance 0.25? cmos technology. the m5m5v408b is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. m5m5v408b is packaged in 32-pin plastic sop, 32-pin plastic tsop and 32-pin 8mm x 13.4mm stsop packages. two types of tsops and two types of stsops are available, m5m5v408btp (normal-lead-bend tsop), m5m5v408brt (reverse-lead-bend tsop), m5m5v408bkv (normal-lead-bend stsop) and m5m5v408bkr (reverse-lead-bend stsop). these two types tsops and two types stsops are suitable for a surface mounting on double-sided printed circuit boards. from the point of operating temperature, the family is divided into three versions; "standard", " w -version", and " i -version". those are summarized in the part name table below. part name table (3.0v, typ.) icc1 * "typical" parameter is sampled, not 100% tested.
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis a 4 a 5 a 6 a 7 a 14 a 16 a 17 vcc a 15 a 18 w a 13 a 8 a 9 a 11 a 12 gnd a 2 a 0 dq1 dq2 dq3 dq5 dq6 dq7 dq8 s a 10 oe a 1 a 3 dq4 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 outline 32p3k-c a 11 a 9 a 8 a 13 a 18 a 15 vcc a 17 a 16 a 14 a 12 a 7 a 6 a 5 a 4 w oe a 10 s dq8 dq7 dq6 dq5 dq4 gnd dq3 dq2 dq1 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 outline 32p3k-b 2 pin configuration (top view) outline 32p3y-j (rt) outline 32p2m-a (fp) 32p3y-h (tp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a 9 oe s a 13 a 8 a 15 dq 6 dq 5 dq 4 dq 8 dq 7 a 11 w v cc a 10 gnd dq 3 dq 2 dq 1 a 12 a 14 a 16 a 18 a 6 a 2 a 3 a 5 a 1 a 0 a 7 a 4 a 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 9 oe s a 13 a 8 a 15 dq 6 dq 5 dq 4 dq 8 dq 7 a 11 w v cc a 10 a 17 gnd dq 3 dq 2 dq 1 a 12 a 14 a 16 a 18 a 6 a 2 a 3 a 5 a 1 a 0 a 7 a 4 m5m5v408bkv m5m5v408bkr
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis function table block diagram 3 mode dq icc s w oe write read h l l l l x l h h h x x non selection high-impedance high-impedance active standby read a 4 a 5 a 6 a 7 a 12 a 14 a 16 a 17 a 18 a 11 a 9 a 8 12 a 0 11 a 1 10 a 2 9 a 3 a 13 25 26 27 28 8 7 6 5 4 3 2 30 1 a 15 31 a 10 23 dq 1 dq 2 dq 3 dq 4 v cc (3v) gnd (0v) w oe dq 5 dq 6 dq 7 dq 8 s 24 13 14 15 17 32 22 18 19 20 21 29 16 a0 ~ a18 dq1 ~ dq8 s w oe vcc gnd address input data input / output chip select input write control input output inable input power supply ground supply pin function data input (d) active active memory array 524288 words x 8 bits clock generator function the m5m5408bfp,tp,rt,kv,kr is organized as 524,288- words by 8-bit. these devices operate on a single +2.7~3.6v power supply, and are directly ttl compatible to both input and output. its fully static circuit needs no clocks and no refresh, and makes it useful. a write operation is executed during the s low and w low overlap time. the address(a0~a18) must be set up before the write cycle a read operation is executed by setting w at a high level and oe at a low level while s are in an active state(s=l). when setting s at a high level, the chips are in a non- selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high-impedance state, allowing or-tie with other chips. setting the oe at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. the power supply current is reduced as low as 0.3?(25?, typical), and the memory data can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. data output (q) 20 19 18 17 1 2 3 4 16 15 14 13 12 11 10 9 6 7 31 32 21 22 23 25 8 30 26 27 28 29 5 24 m5m5v408bkv/kr m5m5v408b fp/tp/rt m5m5v408bkv/kr m5m5v408b fp/tp/rt
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis 4 absolute maximum ratings pf 8 10 v i =gnd, v i =25mvrms, f=1mhz v o = gnd,v o =25mvrms, f=1mhz c i c o symbol parameter limits conditions units ? ma ? ma v icc 1 icc 2 icc 4 v ih v il i o icc 3 v oh1 i oh = -0.5ma v oh2 i oh = -0.05ma v ol i ol =2ma i i v i =0 ~ vcc s=v ih or oe=v ih, v i/o =0 ~ vcc vcc+0.3v 0.6 2.2 -0.3 * 2.4 0.5 0.4 ? 40 30 12 vcc-0.5v ? 7 -hw, -hi max typ min dc electrical characteristics +70? +40 ~ +70? +25 ~ +40? 1.2 0.3 f= 10mhz f= 1mhz - - - - - - - - - - supply voltage input voltage output voltage power dissipation operating temperature storage temperature v mw ? ? conditions ta=25? 700 -20 ~ +85 -65 ~150 ratings v cc v i v o p d t a t stg -0.5 * ~ +4.6 -0.5 * ~ vcc + 0.5 0 ~ vcc symbol parameter units -40 ~ +85 0 ~ +70 standard w- version i- version with respect to gnd f= 10mhz f= 1mhz 5 40 30 7 5 +70 ~ +85? +70 ~ +85? -20 ~ +25? -40 ~ +25? -l, -lw, -li -h, -hw, -hi 0 ~ +25? -h -hw -hi - -lw, -li - - 0.3 0.3 1 1.2 1.2 3.6 - - - - 24 24 48 - (-l, -h) (-lw, -hw) (-li, -hi) with respect to gnd with respect to gnd ( vcc=2.7 ~ 3.6v, unless otherwise noted) high-level input voltage low-level input voltage high-level output voltage 1 high-level output voltage 2 low-level output voltage input leakage current output leakage current active supply current ( ac,mos level ) ( ac,ttl level ) active supply current stand by supply current ( ac,mos level ) ( ac,ttl level ) stand by supply current s 0.2v other inputs 0.2v or 3 vcc-0.2v output-open s=vil other inputs=v ih or v il output-open s=v ,other inputs= 0 ~ vcc s 3 vcc-0.2v other inputs=0~vcc * -3.0v in case of ac (pulse width 30ns) note 1: direction for current flowing into ic is indicated as positive (no mark) note 2: typical value is for vcc=3.0v and ta=25? capacitance (vcc=2.7 ~ 3.6v, unless otherwise noted) symbol parameter conditions limits max typ min units input capacitance output capacitance * -3.0v in case of ac (pulse width 30ns)
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis output disable time after oe high output enable time after s low output enable time after oe low output disable time after s high 5 t cr ns t a (s) t a (oe) t dis (s) t dis (oe) t en (s) t en (oe) t v (a) t a (a) 35 35 100 75 0 85 85 40 0 0 5 5 1ttl cl dq 85 10 5 10 85 85 45 30 30 30 85 60 0 70 70 35 0 0 5 5 t cw t w (w) t su (a) t su (a-wh) t su (s) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) 100 10 5 10 100 100 50 35 35 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns input rise time and fall time reference level output loads 2.7v~3.6v v ih =2.4v,v il =0.4v v oh =v ol =1.5v transition is measured ?00mv from steady state voltage.(for t en ,t dis ) 5ns fig.1,cl=30pf cl=5pf (for ten,tdis) ac electrical characteristics (vcc=2.7 ~ 3.6v, unless otherwise noted) (1) test conditions (2) read cycle symbol parameter limits units max min max min read cycle time address access time chip select access time output enable access time data valid time after address (3) write cycle symbol parameter limits max min max min units write cycle time write pulse width address set up time address set up time with respect to w high chip select set up time data set up time data hold time write recovery time output disable time after w low output disable time after oe high output enable time after w high output enable time after oe low supply voltage input pulse fig.1 output load including scope and jig capacitance m5m5v408b fp,tp,rt,kv,kr-85 m5m5v408b fp,tp,rt,kv,kr-10 m5m5v408b fp,tp,rt,kv,kr-85 m5m5v408b fp,tp,rt,kv,kr-10
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis t en (w) 6 t a (a) t a (s) t v (a) t dis (s) t a (oe) t en (oe) t dis (oe) t cr t h (d) t su (d) dq 1~8 t su (s) t su (a-wh) t en (oe) t dis (oe) t w (w) t rec (w) t su (a) t dis (w) t cw t en (s) w = "h" level a 0~18 dq 1~8 a 0~18 oe oe s w s (4)timing diagrams read cycle (note3) (note3) (note3) (note3) valid data write cycle ( w control mode ) data in stable (note3) (note3)
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis 7 note 3: hatching indicates the state is "don't care". note 4: a write occurs during the overlap of a low s and a low w. note 5: if w goes low simultaneously with or prior to s,the output remains in the high impedance state. note 6: don't apply inverted phase signal externally when dq pin is in output mode. t h (d) t su (d) dq 1~8 t su (s) t rec (w) t su (a) t cw a 0~18 w s write cycle (s control mode) data in stable (note3) (note3) (note4) (note5)
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis 8 t su (pd) t rec (pd) ns 0 5 ms 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) s 3 vcc - 0.2v vcc v v 2.0 vcc (pd) v i (s) icc (pd) 2.0 s -hw, -hi +70? +40 ~ +70? +25 ~ +40? +70 ~ +85? +70 ~ +85? -l, -lw, -li -h, -hw, -hi 0 ~ +25? -lw, -li -20 ~ +25? -40 ~ +25? -h -hw -hi 10 1 0.3 0.3 0.3 1 1 1 3 - - - - 20 20 40 - - - - - - - - ? ? ? ? ? ? ? ? power down characteristics (1) electrical characteristics symbol parameter test conditions limits min typ max units power down supply voltage chip select input s power down supply current vcc=3.0v, s 3 vcc-0.2v, other inputs=0 ~ vcc (2) timing requiremints symbol parameter test conditions limits min typ max units power down set up time power down recovery time (3) timing diagram s control mode typical value is for ta=25?
mitsubishi electric m5m5v408bfp/tp/rt/kv/kr revision-k 1.0 e , ' 98.09.07 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis 9 revision history revision no. history date k0.1e the first edition '98.3.05 preliminary k0.2e added m5m5v408bfp/tp/rt '98.7.30 preliminary k1.0e the first product version '98.9.7
sop32-p-525-1.27 weight(g) jedec code 1.29 eiaj package code lead material alloy 42 32p2m-a plastic 32pin 525mil sop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .35 0 0 .13 0 .55 20 .3 11 .8 13 .6 0 .27 1 .1 0 .75 2 .4 0 .15 0 .75 20 .4 11 .27 1 .1 14 .8 0 .35 1 .34 13 .2 0 .05 3 .5 0 .2 0 .95 20 .5 11 .4 14 .0 1 .15 0 b 2 ?76 0 0 ? e e 1 32 17 16 1 h e e d b e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f mar.?8
tsop 32-p-400-1.27 weight(g) 0.53 jedec code eiaj package code lead material alloy 42 32p3y-h symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters a 1 0.2 0.125 0.76 i 2 0.9 m e 10.36 10 0 0.1 0.8 0.6 0.5 0.4 11.96 11.76 11.56 1.27 10.26 10.16 10.06 21.05 20.95 20.85 0.175 0.125 0.105 0.5 0.4 0.35 1.0 0.05 1.2 e ii plastic 32pin 400mil tsop ( ) detail f recommended mount pad h e e e e y a 2 a 1 l 1 a f m e i 2 b 2 b d l 1 16 17 32 c mar.?8
tsop 32-p-400-1.27 weight(g) 0.53 jedec code eiaj package code lead material alloy 42 32p3y-j plastic 32pin 400mil tsop ( ) symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters a 1 0.2 0.125 0.76 i 2 0.9 m e 10.36 10 0 0.1 0.8 0.6 0.5 0.4 11.96 11.76 11.56 1.27 10.26 10.16 10.06 21.05 20.95 20.85 0.175 0.125 0.105 0.5 0.4 0.35 1.0 0.05 1.2 e ii detail f recommended mount pad h e e e e y a 2 a 1 l 1 a f m e i 2 b 2 b d l 1 16 17 32 c mar.?8
weight(g) jedec code eiaj package code lead material alloy 42 32p3k-b plastic 32pin 8 5 13.4mm tsop ( ) symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h d a 1 m d .15 0 .05 0 .13 0 .7 11 .9 7 .2 13 .4 0 .9 0 .125 0 .0 1 .2 0 .15 0 .8 11 .0 8 .5 0 .4 13 .5 0 .8 0 .2 0 .2 1 .3 0 .2 0 .9 11 .1 8 .6 13 .6 0 .1 0 b 2 i 2 .225 0 .0 12 0 ?0 e recommended mount pad f a d h d e 1 16 17 32 l a 2 c l 1 a 1 l 2 b 2 m d e b e detail f y mar.?8
weight(g) jedec code eiaj package code lead material alloy 42 32p3k-c plastic 32pin 8 5 13.4mm tsop ( ) symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h d a 1 m d .15 0 .05 0 .13 0 .7 11 .9 7 .2 13 .4 0 .9 0 .125 0 .0 1 .2 0 .15 0 .8 11 .0 8 .5 0 .4 13 .5 0 .8 0 .2 0 .2 1 .3 0 .2 0 .9 11 .1 8 .6 13 .6 0 .1 0 b 2 i 2 .225 0 .0 12 0 ?0 e recommended mount pad f a d h d e 1 16 17 32 l a 2 c l 1 a 1 l 2 b 2 m d e b e detail f y mar.?8

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